Area optimized implementation of AES algorithm on FPGA

In today´s digital world, data security is most of the common issue in network security domain. The National Institute of Standards and Technology (NIST) proposes a publication of encryption standards by considering Federal Information Processing Standards (FIPS) publications. The presented paper describes AES (Advanced Encryption Standard)-128 algorithm in optimized manner. This paper produces a design of AES-128 system which produces area optimized design by reducing number of slices per area in CLB(Configurable Logic Blocks).This paper produces a design which uses Block RAM (BRAM) as stored memory for S-BOX(Substitution Box).This reduces the array storing capacity of CLBs.