Low power testing using re-configurable Johnson counter and scalable SIC counter

This paper deals with a low power approach to generate test pattern for Built In Self Test. Test pattern generated using LFSR has high switching activity and thus a single input change vectors are obtained using reconfigurable Johnson counter and Scalable SIC counter. We proposed a unique low transition multiple single input change sequence used to reduce the switching activity. Test per clock and Test per scan scheme are used to simulate the circuit under test at each clock cycle and scan chain respectively to achieve high fault coverage. Simulation results with ISCAS benchmark circuit s27 shows reduction in area and delay thus in test power with targeted fault coverage without increasing the test length.