CORDIC architecture based 2-D DCT and IDCT for image compression

Generally, 2-D DCT/IDCT (Two dimensional discrete cosine transform and its inverse) are widely used in many image processing systems. In this paper, efficient architectures are proposed. These architectures have parallel and pipelined structures which are used to implement 8×8 DCT/IDCT processors. These processors involve two 8-point DCT/IDCT processors along with a dual-bank of SRAM (128 words) and a coefficient ROM (6 words), a control unit and two multiplexers. Here, CORDIC arithmetic is used to design the kernel arithmetic unit (AU). The proposed architectures for 2-D DCT/IDCT not only reduce the power consumption but also simplify the hardware with a very high performance.