A parallel architecture for efficient reverse converter using Chinese remainder theorem

In this paper, we introduced a two level architecture for designing a residue to binary number system converter with a four moduli set that will use Chinese remainder theorem and new Chinese remainder theorem-I algorithms. The multilevel design will help to improve the performance of residue to binary converter. The conversion delay and hardware complexity of proposed residue to binary converter is further reduced by replacing the carry select adder by modified carry select adder with less delay and hardware requirement.