Power efficient dual dynamic flip-flop design featuring embedded logic using CMOS technology

In this paper, we present a dual dynamic flip-flop (DDFF) and a novel embedded logic module (DDFF-ELM) based on DDFF. These proposed designs remove the large capacitance existing in the precharge node by following a split dynamic node structure to independently drive the output pull-up and pull-down transistors. It presents speed efficient method to incorporate complex logic functions into the flip-flop with small delay penalty and reduces the power dissipation by reducing the precharge capacitance. The DDFF offers power and area reduction. The main aim of the DDFF-ELM is to reduce pipeline overhead which arises due to the pipeline setup time, propagation delay and clock skew. It presents an area, power, and speed efficient method to incorporate complex logic functions into the flip-flop. The execution comparisons are made in 180nm and 250nm CMOS technology. A high speed ring counter with clock gating technology using digital CMOS gate logic components by the DDFF structure is also designed which is well suited for modern high performance circuits. The performance improvements indicate that the proposed designs are well suited for modern high-performance designs where power dissipation and latching overhead are of major concern.