• DocumentCode
    3687445
  • Title

    Design of error-compensated fixed-width multiplier

  • Author

    Aniket V. Junghare;Rashmi S. Keote;P. T. Karule

  • Author_Institution
    Department of Electronics Engineering, Yeshwantrao Chavan College of Engineering, Nagpur, India
  • fYear
    2015
  • fDate
    4/1/2015 12:00:00 AM
  • Firstpage
    1675
  • Lastpage
    1678
  • Abstract
    This paper presents an error compensation method for fixed-width multipliers. The analysis for the truncation part is done and accordingly the compensation circuit is made. Here design of 6-bit fixed-width multiplier is done using Xilinx. The simulation results show significant improvement in terms of delay and also save area.
  • Keywords
    "Indexes","Yttrium","Microwave integrated circuits","Complexity theory"
  • Publisher
    ieee
  • Conference_Titel
    Communications and Signal Processing (ICCSP), 2015 International Conference on
  • Type

    conf

  • DOI
    10.1109/ICCSP.2015.7322804
  • Filename
    7322804
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3687445