DocumentCode :
3687447
Title :
An efficient methodology for workload reduction
Author :
P. Anuradha;Hemalatha Rallapalli;G. Narasimha; Syed Musthak Ahmed
Author_Institution :
Electronics &
fYear :
2015
fDate :
4/1/2015 12:00:00 AM
Firstpage :
1684
Lastpage :
1689
Abstract :
Embedded systems are designed as a system-on-chip (SoC) with different processors and memory systems. Workloads on embedded systems are rapidly changing due to high performance demands. System level design space exploration for high performance embedded systems is a very important problem. A very large space of design choices exists for a high performance; embedded system in terms of both processing elements and the memory systems. Exploration of such a large space is intractable. To perform efficient design space exploration for SoCs adopted an approach of workload characterization. Knowing the workload characteristics is very important in the efficient design space for SoCs. The workload characterization approach uses the profiling tools and performance counters to measure the important metrics that determine the performance bottlenecks of a processor. This has to done as most important and dominant parameters are not known and after measuring important metrics, a statistical technique of characterization called Principle Component Analysis is used. PCA identifies dominant independent variables which help to do workload characterization. Using such data, generating workload performance models are generated and then those are fed to a system level simulator to analyze the design. This paper shows workload characterization for multi core and single core processors to the SPEC CPU 2000 benchmarks.
Keywords :
"Principal component analysis","Benchmark testing","Correlation","Data models","Analytical models","Microarchitecture","Standards"
Publisher :
ieee
Conference_Titel :
Communications and Signal Processing (ICCSP), 2015 International Conference on
Type :
conf
DOI :
10.1109/ICCSP.2015.7322806
Filename :
7322806
Link To Document :
بازگشت