DocumentCode :
3687469
Title :
Design high security AES with fault detection countermeasure
Author :
Yashashri V. Bele;Yogesh A. Suryavanshi
Author_Institution :
Department of Electronics engineering (VLSI Design), Yeshwantrao Chavan College of Engineering, an autonomous institute affiliated to Rashtrasant Tukadoji Maharaj Nagpur University, Maharashtra India
fYear :
2015
fDate :
4/1/2015 12:00:00 AM
Firstpage :
1777
Lastpage :
1781
Abstract :
Cryptography is a method that has been developed to ensure security of messages and transfer of data. Advanced Encryption Standard (AES) is the first choice for many critical applications. The AES is a Federal Information Processing Standard (FIPS) which is cryptographic algorithm used to protect electronic data. Implementations of the Advanced Encryption Standard (AES) have rapidly grown in various applications including telecommunications, finance and networks that require low power consumptions, low cost design, less delay and especially it should be more secured. In this paper, the implementation details of the AES 128-bit Encryption and Decryption are presented. Area required, Delay, Power for conventional Encryption and Decryption is calculated. To reduce area required and Delay, We have done the parallel implementation of S-box and Area, Delay is compared with the conventional Encryption. We conduct a fault injection attack and fault detection. To protect AES, We apply Proposed Fault Detection scheme to AES Encryption structure and compare its Area, Throughput and Frequency and Results show that the parameters like Area, Throughput, Frequency have been improved.
Keywords :
"Cryptography","Delays","Throughput","Table lookup","Information processing","Standards"
Publisher :
ieee
Conference_Titel :
Communications and Signal Processing (ICCSP), 2015 International Conference on
Type :
conf
DOI :
10.1109/ICCSP.2015.7322828
Filename :
7322828
Link To Document :
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