SoC based test bed design for OBC interfaces

Due to the current demand for faster and large number of satellite realization, test bed plays the fundamental role for developing high fidelity space systems. Our work is based on a new test system architecture called Modular Test System (MTS) architecture for rapid realization of on-board computer (OBC) packages. This envisages standardization, miniaturization, easy re- workability, greater portability of test system and better harness management. In the proposed design of MTS, SmartFusion customizable system-on-chip(c-SoC) is used as the Front end processing (FEP) unit. In this paper, emulation of port reading/writing operation from the simulation units by FEP has been discussed. Additionally the data is monitored on the host terminal through Ethernet and Universal Asynchronous Receiver Transmitter (UART) interfaces. Hence, MTS results in a single PC based test system and require minimal changes for different missions including interplanetary, communication, navigation and remote sensing. In this paper we present the methodology and explanation of components /entities involved in implementing the I/O operations, UART and Ethernet interfaces.