DocumentCode :
3687514
Title :
SAR-ADC design for neural recording system with energy efficient quaternary capacitive DAC switching scheme
Author :
Rahul Bire;Somulu Gugulothu
Author_Institution :
Yeshwantrao Chavan College Of Engineering, An Autonomous Institution Affiliated to RTM Nagpur University, India
fYear :
2015
fDate :
4/1/2015 12:00:00 AM
Firstpage :
228
Lastpage :
232
Abstract :
This paper presents energy efficient 4-bit successive approximation register analog to digital converter (SAR-ADC) for neural recording front end interface of neural prosthetic system(Brain machine interface). The energy efficient quaternary capacitive switching scheme (QCS) in the implementation of capacitive digital to analog converter (C-DAC) is employed which makes the energy consumption in the C-DAC independent of the output digital code. The proposed technique achieves a 50% reduction in the average energy consumption. The design is implemented in 0.25um standard complementary metal-oxide semiconductor technology (CMOS).
Keywords :
"Switches","Energy efficiency","Approximation methods","Registers","Transient analysis","Prosthetics","MOS devices"
Publisher :
ieee
Conference_Titel :
Communications and Signal Processing (ICCSP), 2015 International Conference on
Type :
conf
DOI :
10.1109/ICCSP.2015.7322874
Filename :
7322874
Link To Document :
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