DocumentCode
3687631
Title
A cache- and memory-aware mapping algorithm for big data applications
Author
Thomas Canhao Xu;Ville Leppänen
Author_Institution
Department of Information Technology, University of Turku, Turku, Finland
fYear
2015
Firstpage
110
Lastpage
115
Abstract
In this paper, we propose and investigate a task mapping algorithm for big data applications. As a critical resource, data are produced faster than ever before. Parallel programs that process these data on massive parallel systems are widely adopted. The task mapping algorithm however, has not been well optimized for these applications. We explore the characteristics of big data applications based on a shared cache/memory multicore processor. The latencies of cache and memory sub-systems are analysed. The proposed algorithm is designed to optimize the cache/memory latency, as well as intra-application latency. We introduce an efficient greedy algorithm to calculate the mapping result based on the congregate degree of nodes. Different numbers of search spaces are discussed and evaluated. Experiments are conducted based on synthetic simulation and running real applications on a full system simulation environment. Results confirmed the effectiveness of the proposed algorithm. Average execution time of five selected big data applications is reduced by 8% compared with the first fit algorithm.
Keywords
"Big data","Multicore processing","Algorithm design and analysis","Measurement","Artificial intelligence","Databases","Greedy algorithms"
Publisher
ieee
Conference_Titel
Digital Information Processing and Communications (ICDIPC), 2015 Fifth International Conference on
Type
conf
DOI
10.1109/ICDIPC.2015.7323015
Filename
7323015
Link To Document