Dual threshold bit-swapping LFSR for power reduction in BIST

This paper proposes a novel idea for incorporating dual threshold voltage for Bit swapping LFSR (BS-LFSR) in order to obtain highly power efficient pattern generators for built in self-test (BIST) based VLSI architecture. BIST is a hardware entity, which is capable of testing the circuit during manufacturing as well as in situ conditions. It make use of different types of random generators for test vector generation to achieve maximum fault coverage. VLSI testing field demands low power designs for test pattern generation, as the device dimensions are shrinking drastically and most of them are made to be battery operated (portable devices). Current trends in test pattern generation make use of random pattern generator such as scan chain based generators, counter based circuits and Linear Feedback Shift Registers (LFSR) in which LFSR found to be common. In order to reduce the transition power due to high switching activity in test vector generation, the Bit-Swapped LFSR based pattern generators are used. Bit swapping LFSR will generate random test sequence with low switching power by finding the hamming distance between two adjacent patterns and it minimizes the hamming distance by utilizing a combinational logic. But the average power still remains high, for this reason an alternate design methodology is proposed. In the proposed design a convenient reduction in power is attained by providing dual threshold voltages to BS-LFSR architectures. All the above discussed BISTs were verified with a custom designed Circuit Under Test (CUT), defined in software simulators and the result seems to be encouraging.