CNFET based 8-T SRAM cell to improve stability with reduced power consumption

Deviations in local and global process parameters causes increase in threshold voltage (V_t) variation in ultra-short channel devices, such as CMOS. Thus, it is impossible to operate the CMOS based 6-Transistor (6T) SRAM cell bellow 600 mV. Hence, a CNFET based 8T SRAM cell is suggested in this article to alleviate the effect of process fluctuations. Different design metrics of an SRAM cell are accessed for the proposed cell and to show its effectiveness, the design metrics are compared with its conventional counterpart. The proposed cell dissipates less dynamic power (1.2× read power and 1.02× write power) and also consumes 16.17× less power when it is not accessed @ 200 mV compared to conventional CMOS based 8T cell. It depicts its robustness against process fluctuations by showing narrower spread in read power (97.91%), write power (96.35%), and hold power consumption (87.34%) for the same supply voltage. The proposed CNFET based 8T cell shows 59.41% higher read stability @ 400 mV than the CMOS based 8T SRAM cell.