SPDT Switch Using Both nMOS and pMOS Transistors for Improving Power Handling

An SPDT switch consisting of both nMOS and pMOS transistors is presented. Compared with conventional SPDT switches using only nMOS transistors under the same bias condition, the proposed switch exhibits better power-handling capability (PHC). The mechanism for the PHC improvement is explained. A prototype is implemented using a 0.18-um CMOS process. Measurement results show that, at 2.4 GHz, the insertion loss is 0.62 dB when the nMOS transistors are on and 0.91 dB when the pMOS transistors are on. For both modes, the measured return loss and isolation are better than 10 dB and 19 dB, respectively, up to 6 GHz. Under 1.8-V operation, the switch is able to handle a 26.1-dBm input power when the nMOS transistors are on and a 24.0-dBm input power when the pMOS transistors are on.