• DocumentCode
    3689020
  • Title

    Metal gate VT modulation using PLAD N2 implants for Ge p-FinFET applications

  • Author

    Shraddha Kothari;Chandan Joishi;Dhirendra Vaidya;Hasan Nejad;Benjamin Colombeau;Swaroop Ganguly;Saurabh Lodha

  • Author_Institution
    Dept of Electrical Engineering, IIT Bombay, Powai, Mumbai, India- 400076
  • fYear
    2015
  • Firstpage
    214
  • Lastpage
    217
  • Abstract
    This work reports multi-VT Ge gate stacks using low energy plasma-assisted doping (PLAD) with N2 for Ge p-FinFET applications. Varying implant dose and energy is used to demonstrate effective TiN work-function tuning over a range of 170 mV from near-midgap to near-valence band edge of Ge without significant impact on gate capacitance (effective oxide thickness (EOT)), interface quality and TiN resistance. However, unlike Si gate stacks, increased gate leakage in implanted samples is likely due to traps created in the HfO2 Hi-k layer and exposed to channel carriers due to a low band offset GeO2 interfacial layer.
  • Keywords
    "Logic gates","Tin","Implants","Hafnium compounds","Gate leakage","Silicon"
  • Publisher
    ieee
  • Conference_Titel
    Solid State Device Research Conference (ESSDERC), 2015 45th European
  • ISSN
    1930-8876
  • Print_ISBN
    978-1-4673-7133-9
  • Electronic_ISBN
    2378-6558
  • Type

    conf

  • DOI
    10.1109/ESSDERC.2015.7324753
  • Filename
    7324753