• DocumentCode
    3689021
  • Title

    The defect-centric perspective of device and circuit reliability — From individual defects to circuits

  • Author

    B. Kaczer;J. Franco;P. Weckx;Ph. J. Roussel;E. Bury;M. Cho;R. Degraeve;D. Linten;G. Groeseneken;H. Kukner;P. Raghavan;F. Catthoor;G. Rzepa;W. Goes;T. Grasser

  • Author_Institution
    imec, Kapeldreef 75, B-3001 Leuven, Belgium
  • fYear
    2015
  • Firstpage
    218
  • Lastpage
    225
  • Abstract
    As-fabricated (time-zero) variability and mean device aging are nowadays routinely considered in circuit simulations and design. Time-dependent variability (reliability variability) is an emerging trend that needs to be considered in circuit design as well. This phenomenon in deeply scaled devices can be best understood within the so-called defect-centric picture in terms of an ensemble of individual defects and their time, voltage, and temperature dependent properties. The properties of gate oxide defects are discussed and it is shown how these properties can be used to construct time-dependent variability distributions and can be propagated up to transistor-level circuits.
  • Keywords
    "Logic gates","Stress","Degradation","Integrated circuit reliability","Field effect transistors","Integrated circuit modeling"
  • Publisher
    ieee
  • Conference_Titel
    Solid State Device Research Conference (ESSDERC), 2015 45th European
  • ISSN
    1930-8876
  • Print_ISBN
    978-1-4673-7133-9
  • Electronic_ISBN
    2378-6558
  • Type

    conf

  • DOI
    10.1109/ESSDERC.2015.7324754
  • Filename
    7324754