DocumentCode :
3689022
Title :
Experimental evidences and simulations of trap generation along a percolation path
Author :
Louis Gerrer;Razaidi Hussin;Salvatore M. Amoroso;J. Franco;P. Weckx;M. Simicic;N. Horiguchi;Ben Kaczer;T. Grasser;Asen Asenov
Author_Institution :
Device Modeling Group, University of Glasgow, G12 8LT, Glasgow, UK
fYear :
2015
Firstpage :
226
Lastpage :
229
Abstract :
In this paper we present experimental results of single trap impact on bulk MOSFETs, shedding light on counter intuitive behavior when increasing the gate bias. Using a well calibrated 3D TCAD model, statistical simulations at atomistic level are performed, demonstrating that the interactions between the traps and the percolation path are responsible for the unexpected bias dependences of the trap impact and therefore that a trap generation enhanced by higher current densities along this path can explain measured data.
Keywords :
"Logic gates","Integrated circuit modeling","Current density","Integrated circuit reliability","Nanoscale devices","MOSFET"
Publisher :
ieee
Conference_Titel :
Solid State Device Research Conference (ESSDERC), 2015 45th European
ISSN :
1930-8876
Print_ISBN :
978-1-4673-7133-9
Electronic_ISBN :
2378-6558
Type :
conf
DOI :
10.1109/ESSDERC.2015.7324755
Filename :
7324755
Link To Document :
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