Thin-film SOI PIN-diode leakage current dependence on back-gate-potential and HCI traps

We investigated the leakage current of thin film silicon-on-insulator (SOI) pin-diodes in dependence of the back-gate potential and hot carrier induced traps. Leakage current of virgin and hot-carrier stressed diodes was measured at distinct back-gate potentials. TCAD simulations were used to determine the mechanisms of leakage current generation at specific back-gate potentials. Traps were introduced to study the impact of hot-carrier stress on the leakage current. Location, polarity and density of traps were considered. For a virgin device tunneling is predominant in inversion and accumulation. In full depletion surface generation dominates the leakage behavior. Surface and oxide traps shift the leakage current and alter its mechanism with increasing density, i.e. stress time. In inversion trap generation dominates at the top SOI interface. In depletion top and bottom interface traps are generated.