Automatic debug circuit for FPGA rapid prototyping

In the modern verification environment the FPGA-based prototyping has become an important part of the whole verification flow. The ability to simulate real time application in the more realistic speeds allows much higher coverage than traditional HDL logic simulators. The main disadvantage of FPGA prototyping is inability to inspect and observe internal FPGA signals. Currently the only commercial solution for this problem is using embedded trace-buffers to record subsets of internal signals. This requires that the problem is first detected and then designer can implement additional trace-buffers and make new synthesis. This paper, presents an automatic debug circuit which allows easy access and extraction of all internal signals. The debug circuit is built on a remaining FPGA resources so it´s important that this does not have a negative effect on the FPGA performance. The experiments showed that the automatic debug circuit does not significantly reduces FPGA performance and that it can be used for FPGA rapid prototyping.