DocumentCode :
3689812
Title :
Advanced integrated metallization enables 3D-IC TSV scaling
Author :
Jengyi Yu;Sanjay Gopinath;Praveen Nalla;Matthew Thorum;Larry Schloss;Daniela M. Anjos;Prashant Meshram;Greg Harm;Joe Richardson;Tom Mountsier
Author_Institution :
Lam Research Corp 4400 Cushing Parkway, Fremont, CA, USA
fYear :
2015
fDate :
5/1/2015 12:00:00 AM
Firstpage :
205
Lastpage :
208
Abstract :
Innovative solutions have been developed to address the challenges of through-silicon via (TSV) metallization with small sizes and high aspect ratios. We demonstrate an advanced metallization scheme including conformal film depositions of metal barrier and seed with excellent sidewall coverage to achieve void-free Cu fill in small-size (10 to 1 μm) TSV with high aspect ratio (10:1 to 20:1). In addition, it reduces the field metal thickness to significantly lower the costs of metallization and subsequent CMP. TSVs fabricated using this new process integration scheme exhibited higher breakdown voltage and lower leakage current than those made with the conventional PVD barrier seed. No degradation in performance was observed after 400°C annealing and thermal cycling. The improved performance is attributed to the formation of pinhole-free metal barrier layer with excellent sidewall coverage.
Keywords :
"Decision support systems","Metallization","Fabrication","Market research","Three-dimensional displays"
Publisher :
ieee
Conference_Titel :
Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM), 2015 IEEE International
ISSN :
2380-632X
Electronic_ISBN :
2380-6338
Type :
conf
DOI :
10.1109/IITC-MAM.2015.7325620
Filename :
7325620
Link To Document :
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