IP cores for hardware acceleration of decision tree ensemble classifiers

This paper proposes four different hardware architectures for parallel implementation of decision trees forming an ensemble classifier are presented. Proposed architectures can accelerate ensemble classifiers composed of axis-parallel, oblique and nonlinear decision tree (DTs). Hardware architectures for the implementation of a number of combination rules are also presented, enabling the complete ensemble classifier hardware accelerators. Conducted experiments, based on 29 UCI datasets, indicate that the Field Programmable Gate Array (FPGA) implementations based on proposed architectures offer significant improvement in the instance classification time in comparison with the traditional software implementations.