Turbo decoder design for high code rates

Turbo decoders for modern wireless communication systems are required to support a wide range of code rates. The maximum supported code rate has strong impact on the choice of turbo decoder algorithm and architecture. This paper explores the problem of achieving high performance with turbo decoders at high code rates, and provides solutions on algorithmic and architectural level. A standard-compliant turbo decoder ASIC prototype for 3GPP Evolved EDGE has been implemented in 0.18 µm CMOS, and corresponding measurements proof the results of our analysis.