DocumentCode :
3694082
Title :
100 Gbit/s authenticated encryption based on quantum key distribution
Author :
Michael Muehlberghuber;Christoph Keller;Norbert Felber;Christian Pendl
Author_Institution :
ETH Zurich, Integrated Systems Laboratory (IIS), Gloriastrasse 35, 8092, Switzerland
fYear :
2012
Firstpage :
123
Lastpage :
128
Abstract :
We propose a block-cipher-based hardware architecture for authenticated encryption (AE) applications supporting the Ethernet standard IEEE 802.3ba. Our main design goal was to achieve high throughput on FPGA platforms. Compared to previous works aiming at data rates beyond 100 Gbit/s, our design makes use of an alternative block cipher and an alternative mode of operation, namely Serpent and the offset codebook mode of operation, respectively. Using four cipher cores for the encryption part of the AE architecture, we achieve a throughput of 133 Gbit/s on an Altera Stratix IV FPGA. The design requires 30 kALMs and runs at a maximum clock frequency of 260 MHz. This represents, to the best of our knowledge, the fastest full implementation of an AE scheme on FPGAs to date.
Keywords :
"Ciphers","Encryption","Throughput","Field programmable gate arrays","Computer architecture","Hardware"
Publisher :
ieee
Conference_Titel :
VLSI and System-on-Chip, 2012 (VLSI-SoC), IEEE/IFIP 20th International Conference on
Print_ISBN :
978-1-4673-2658-2
Type :
conf
DOI :
10.1109/VLSI-SoC.2012.7332088
Filename :
7332088
Link To Document :
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