Title :
A physical design study of fabscalar-generated superscalar cores
Author :
Niket K. Choudhary;Brandon H. Dwiel;Eric Rotenberg
Author_Institution :
Department of Electrical and Computer Engineering, North Carolina State University, USA
Abstract :
FabScalar is a recently published tool for automatically generating superscalar cores, of different pipeline widths, depths and sizes. The output of FabScalar is a synthesizable register-transfer-level (RTL) description of the desired core. While this capability makes sophisticated cores more accessible to designers and researchers, meaningful applications require reducing RTL descriptions to physical designs. This paper presents the first systematic physical design study of FabScalar-generated superscalar cores.
Keywords :
"Physical design","Random access memory","Pipelines","Registers","Pipeline processing","Memory management","Latches"
Conference_Titel :
VLSI and System-on-Chip, 2012 (VLSI-SoC), IEEE/IFIP 20th International Conference on
Print_ISBN :
978-1-4673-2658-2
DOI :
10.1109/VLSI-SoC.2012.7332095
