Using asymmetric layer repair capability to reduce the cost of yield enhancement in 3D stacked memories

Three-dimensional (3D) technology makes it possible to organize memories as cell arrays stacked on logic where upper die layers contain the cell arrays and the bottom layer implements the peripheral logic. This creates new degrees of freedom that can be exploited to optimize the use of spare rows/columns to maximize yield. This paper proposes a new idea that exploits an additional degree of freedom that has not previously been utilized which is that the order of the die in the stack can be selected. The cell array dies can be ordered with the one with the most defective cells at the lowest layer, followed by next most defective, and so forth finishing with the die with the fewest defective cells on the top layer. All the cell array dies have identical designs and are manufactured identically. However, the peripheral logic die is designed in a way where it costs less to provide repair on the lower layers than it does on the higher layers of the cell arrays. This is done by limiting the domain over which some spares can be used thereby reducing the number of fuses needed for configuring the spare. Results in the paper show that the ability to skew repair capability across the different layers in a 3DIC allows greater yield enhancement at lower cost both in terms of number of spares and number of fuses.