Title :
Evaluation of fault tolerant technique based on homogeneous FPGA architecture
Author :
Yuki Nishitani;Kazuki Inoue;Motoki Amagasaki;Masahiro Iida;Morihiro Kuga;Toshinori Sueyoshi
Author_Institution :
Graduate School of Science and Technology, Kumamoto University, 2-39-1 Kurokami, Chuo-ku, 860-8555, Japan
Abstract :
FPGA fault detection consumes a great deal of test time compared with ASICs because FPGAs have complex structures. Re-placement and re-routing must be performed to avoid fault points, which causes an increase in recovery time and degrades performance. Therefore, we propose a fault detection method and develop placement and routing tools to avoid fault sources in tile and multiplexer level avoidance, respectively. In the evaluation, the detection method diagnosed a faulty multiplexer with six test configurations. We found that the performance of a faulty FPGA slightly decreased by 2% compared with a normal FPGA in multiplexer level avoidance.
Keywords :
"Field programmable gate arrays","Snow"
Conference_Titel :
VLSI and System-on-Chip, 2012 (VLSI-SoC), IEEE/IFIP 20th International Conference on
Print_ISBN :
978-1-4673-2658-2
DOI :
10.1109/VLSI-SoC.2012.7332105