DocumentCode :
3694103
Title :
Trinocular disparity processor using a hierarchic classification structure
Author :
Andy Motten;Luc Claesen;Yun Pan
Author_Institution :
Expertise Centre for Digital Media, Hasselt University - tUL - IBBT, Wetenschapspark 2, 3590 Diepenbeek, Belgium
fYear :
2012
Firstpage :
247
Lastpage :
250
Abstract :
This paper presents a real-time trinocular disparity processor. The core module performs a pairwise segmented window matching for both the center-right and center-left image pair as their scaled down image pairs. The resulting cost functions are combined which results into nine different curves. A hierarchical classifier is presented which selects the most promising disparity value using information provided by the calculated cost curves and the pixels spatial neighborhood using a two level classification architecture. The disparity processor has been evaluated with an indoor dataset and with a real-time implementation using an FPGA and three cameras. Special care has been taken to reduce the memory footprint so that the processor doesn´t need external memory.
Keywords :
"Cameras","Streaming media","Image color analysis","Clocks","Real-time systems","Classification algorithms","Hardware"
Publisher :
ieee
Conference_Titel :
VLSI and System-on-Chip, 2012 (VLSI-SoC), IEEE/IFIP 20th International Conference on
Print_ISBN :
978-1-4673-2658-2
Type :
conf
DOI :
10.1109/VLSI-SoC.2012.7332109
Filename :
7332109
Link To Document :
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