Reliability study on system memories of an iterative MIMO-BICM system

Technology scaling leads to a decreasing reliability of the fabricated CMOS circuits. Designing reliable applications on unreliable circuitry is one of the big challenges of the next technology generations. Exploiting the knowledge of multiple abstraction layers from circuit and micro-architecture up to algorithm and application layer is key to minimizing dependability cost in terms of area, energy and performance. Fortunately, many applications dealing with imprecise information have an inherent error resilience. Therefore, it is mandatory to analyze the algorithmic error resilience of such applications and to find low-complexity protection methods. In this paper, we present the first study of the impact of hardware errors in the system memories of an iterative MIMO-BICM receiver. We classify the memories in different groups due to their robustness and compare resilience actuators on software, hardware and technology level to combat the hardware errors.