FPGA power reduction by guarded evaluation considering physical information

We reconsider guarded evaluation as a means to reduce FPGA dynamic power consumption. We augment and evaluate guarded evaluation as proposed in [1] after different stages of the FPGA CAD flow. Guarding later in the flow provides more feedback to the algorithm and yields a more effective cost-benefit analysis of newly added signals. Numerical results show that guarding later in the flow yields slightly less power savings versus guarding after technology mapping. However, fewer guards are inserted which results in fewer netlist changes and less impact on routing resource usage.