A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm

An eight transistor static random access memory cell with an access transistor-less architecture is presented that shows high soft error robustness and low leakage current. A 32kb memory array is designed in 65 nm CMOS process. The cell provides 5.6x better immunity to soft errors when compared to a conventional SRAM cell. The cell shows 9.4x smaller read current than a 6T SRAM cell. The featured cell also shows read and write margin improvements.