DocumentCode :
3694826
Title :
A −1.8V to 0.9V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology
Author :
Davide Rossi;Antonio Pullini;Michael Gautschi;Igor Loi;Frank Kagan Gurkaynak;Philippe Flatresse;Luca Benini
Author_Institution :
University Of Bologna, Bologna, Italy
fYear :
2015
Firstpage :
1
Lastpage :
3
Abstract :
A 4-core cluster fabricated in low power 28nm UTBB FD-SOI conventional well technology is presented. The SoC architecture enables the processors to operate “on-demand” on a 0.44V (1.8MHz) to 1.2V (475MHz) supply voltage wide range and −1.2V to 0.9V body bias wide range achieving the peak energy efficiency of 60 GOPS/W, (419μW, 6.4MHz) at 0.5V with 0.5V forward body bias. The proposed SoC energy efficiency is 1.4x to 3.7x greater than other low-power processors with comparable performance.
Keywords :
Decision support systems
Publisher :
ieee
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE
Type :
conf
DOI :
10.1109/S3S.2015.7333483
Filename :
7333483
Link To Document :
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