Negative capacitance in ferroelectric materials and implications for steep transistors

It is now well recognized that energy dissipation in microchips may ultimately restrict device scaling — the downsizing of physical dimensions that has fueled the fantastic growth of microchip industry so far. This is due to the fact that the Boltzmann distribution dictates that, to affect an order of magnitude increase in the drain current, the gate voltage needs to change by at least by 60 mV at room temperature. In practice, a voltage many times this limit of 60 mV has to be applied to obtain a good ratio of the ON and the OFF currents. In fact, the power supply voltage has been stuck at around 1 V for two decades now. On the other hand, continuous down scaling is putting an even larger number of devices in the same area thereby increasing the energy dissipation density beyond controllable and sustainable limits. It has been predicted that unless new principles are found based on fundamentally new physics, the transistors will die a thermal death [1]. In 2008, Salahuddin et al. championed the concept of negative differential capacitance, which, when used as a gate insulator in a MOSFET, could reduce the subthreshold swing below the fundamental limit of 60 mV/decade [2]. In comparison to a conventional transistor, the electrostatic gating in a negative capacitance field-effect transistor is altered in such a way that a small change in the gate voltage creates a larger change in the surface potential. The basic principle of such ‘active’ gating relies on the ability to drive the ferroelectric material away from its local energy minimum to a non-equilibirum state where its capacitance is negative and stabilizing it there by adding a series capacitance. Over the last couple of years, multiple experimental demonstrations have established this concept from both fundamental and technological point of view. In this talk, we will discuss the conceptual background and recent experimental and simulation studies regarding this concept.