Single-well design in FDSOI technology: Towards energy-efficient ultra-wide voltage range digital circuits

This paper demonstrates that the Single Well option offered by the FDSOI technology enables to design energy-efficient digital circuits operating on an ultra-wide voltage range. Silicon measurements of a DSP test chip fabricated in the 28nm node show performance ranging from 2.2GHz at 1.3V down to 65MHz at 440mV. Compared to a full LVT implementation, the leakage power is reduced by up to 6x, for a performance penalty of less than 10%. Additionally, balancing the n-MOS/p-MOS trees over this large voltage range only requires a single back-bias voltage, thus simplifying the power management scheme.