DocumentCode :
3694837
Title :
Engineered substrates for Moore and more than Moore´s law: Device scaling: Entering the substrate era
Author :
Christophe Maleville
Author_Institution :
SOITEC SA, Bernin, France
fYear :
2015
Firstpage :
1
Lastpage :
5
Abstract :
Since 10 years, end markets drastically changed towards mobile connected users and typical performance/cost KPIs have evolved towards more demanding PPAC (Power Performance Area Cost) metrics adding power consumption (battery life) and area (form factors) constraints. In this effort to bring more performance, less power or more functionality, innovation or evolution starting from substrates has demonstrated significant successes, such as FDSOI for extension of Moore´s law beyond 28nm node. In the field of front end modules (FEM) for smartphones, switch, previously built on AsGa substrates, are now built on RFSOI substrates. These examples are perfect illustrations that engineered substrates era is supporting the extension of Moore and More Than Moore roadmaps.
Keywords :
"Substrates","Silicon","Performance evaluation","Radio frequency","Switches","Conductivity","Technological innovation"
Publisher :
ieee
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE
Type :
conf
DOI :
10.1109/S3S.2015.7333494
Filename :
7333494
Link To Document :
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