Emerging 3DVLSI: Opportunities and challenges

As the semiconductor industry continues to drive the CMOS scaling roadmap, traditional cost reduction and the accompanied power/performance/area (PPAC) advantages of successive technology nodes are diminishing to a myriad of process integration challenges and increasing variability, reliability, power and thermal constraints. 3D technologies have been explored as potential alternatives to address various system integration needs and to extend the economic scaling roadmap. Among them, 3D VLSI (3DV) technologies emerge as the most plausible candidates. Unlike packaging-driven 3D technologies (e.g., 2.5D, TSV-based 3D, etc.), the emerging 3DV offers over 1000X more vertical connections approaching the same order of magnitude as 2D VLSI vias. Such a high density of vertical interconnects allows us to envision a cost effective 3D system-on-chip (3D SoC) solution that integrates digital, analog, RF, sensors, power etc. into a single chip device, further expand the PPAC roadmap and drive the next wave of semiconductor growth in the emerging markets of internet of everything (IoE), electronic health (eHealth) and electronic medical (eMedic). In this article, we will discuss the 3DV integration opportunities and associated design and technology challenges.