DocumentCode :
3694853
Title :
On the T-RAM and FED-RAM memory mechanism
Author :
Ahmad Z. Badwan;Qiliang Li;Dimitris E. Ioannou
Author_Institution :
Electrical and Computer Engineering Department, George Mason University, Fairfax, VA 22030 USA
fYear :
2015
Firstpage :
1
Lastpage :
2
Abstract :
We take a closer look on the memory mechanism (“store”) of the T-RAM and FED-RAM memory cells, with the help of extensive numerical simulations. The resulting carrier profiles demonstrate that the accepted interpretation of the memory mechanism as the accumulation (“1”) or depletion (“0”) of holes, under the gate above the p-base, is incorrect. Instead, it is the state (equilibrium or not) of the depletion regions on the sides of the p-base, that determine the stored state of the cell.
Keywords :
"Logic gates","Thyristors","Random access memory","Writing","PIN photodiodes","Transient analysis","Junctions"
Publisher :
ieee
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE
Type :
conf
DOI :
10.1109/S3S.2015.7333510
Filename :
7333510
Link To Document :
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