Title :
Analog performance improvement of self-cascode structures composed by UTBB transistors using back gate bias
Author :
R. T. Doria;R. Trevisoli;M. de Souza;M. A. Pavanello;D. Flandre
Author_Institution :
Electrical Engineering Department, Centro Universitá
Abstract :
This paper explores the use of the back gate bias to enhance the analog performance of self-cascode structures composed by 25nm-long UTBB SOI MOSFETs. It is shown, for the first time, that the use of back gate bias can improve the intrinsic voltage gain by 15 dB, making it larger than the one presented by a 50nm-long single device.
Keywords :
"Transistors","Decision support systems","Silicon","Periodic structures","Solids","Liquids","CMOS integrated circuits"
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE
DOI :
10.1109/S3S.2015.7333512
