Analysis of deeply scaled multi-gate devices with design centering across multiple voltage regimes

This work aims at finding a design-centered FinFET model with small geometric for circuit and system level simulations and performance prediction of next-generation systems on chip. A number of devices including the ITRS 7nm multi-gate device are used as examples. While adjusting design parameters for the transistors, a design centering step is included in which the gate workfunction is carefully adjusted to account for the increased power dissipation due to gate length variations. Using a cross-layer framework, compact device models and standard cell libraries are built up for circuit-level and system-level simulations. Simulation results of SRAM cells as well as some combinational/sequential benchmark circuits are shown to compare the device performance in different technologies.