Title :
Opportunities and challenges of nanowire-based CMOS technologies
Author :
S. Barraud;M. Cassé;L. Gaben;P. Nguyen;J. M. Hartmann;M. P. Samson;V. Maffini-Alvaro;C. Tabone;C. Vizioz;C. Arvet;P. Pimenta-Barros;F. Glowacki;N. Bernier;O. Rozeau;M. A. Jaud;S. Martinie;J. Laccord;F. Allain;B. De Salvo;M. Vinet
Author_Institution :
CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France
Abstract :
The Nano Wire (NW) CMOS technology is widely considered as a promising evolutionary solution of current FinFET technology. The main advantage of the nanowire transistors for ultimate CMOS scaling is their optimal electrostatic confinement. In this paper, the major assets of NW field-effect-transistors in leading-edge technology nodes are explained in details. For this purpose, electron (hole) transport properties of Si (SiGe) NWs and the critical contribution of strain are discussed. A particular attention is given to the key technological integration challenges to be addressed, with emphasis on the practical implementation of 3D high-density stacked-NWs architectures.
Keywords :
"Silicon","Wires","Strain","FinFETs","CMOS integrated circuits","CMOS technology"
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE
DOI :
10.1109/S3S.2015.7333520
