A soft error tolerant 4T gain-cell featuring a parity column for ultra-low power applications

Embedded memories often constitute over 50% of the total silicon area and are the main consumer of static power in ultra-low power (ULP) applications. Operation at sub-threshold supply voltages can significantly reduce the power dissipation of memory arrays, however it also results in lower noise margins and much higher susceptibility to radiation effects, such as soft errors or single event upsets (SEU).