• DocumentCode
    3694870
  • Title

    Subthreshold capable, asynchronous FPGA in a 14nm SOI process

  • Author

    Brian Degnan;Jennifer Hasler

  • Author_Institution
    The Georgia Institute of Technology
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    We have designed a subthreshold-enabled FPGA (seFPGA) that has been sent for fabrication. The seFPGA has a general purpose, but asynchronous architecture that contains 50,880 16-bit LUTs with 4 voltage domains. Furthermore, the architecture is appropriate for the floating-gate or SRAM state storage.
  • Keywords
    "Table lookup","Field programmable gate arrays","Layout","Pipelines","Clocks","Random access memory","Fabrics"
  • Publisher
    ieee
  • Conference_Titel
    SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE
  • Type

    conf

  • DOI
    10.1109/S3S.2015.7333527
  • Filename
    7333527
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3694870