A 300nW near-threshold 187.5–500 kHz programmable clock generator for ultra low power SoCs

We present a 187kHz to 500kHz ADPLL-based clock generator that consumes 300nW from a 0.5V VDD, has a jitter <0.1% and was implemented in a 0.13μm CMOS process. The entire ADPLL was implemented using standard digital design flows and automatic place and route (APR). Moreover, an integrated crystal oscillator (31.25 kHz) is included and serves as the reference for the PLL. Therefore, this is a complete clocking solution for ultra-low power near-threshold SoCs.