Title :
Impact of source/drain silicon cap on FDSOI SiGe pMOSFET performance
Author :
E. Augendre;S. Maitrejean;B. De Salvo;L. Grenouillet;R. Wacquez;M. Vinet;O. Faynot;P. Morin;N. Loubet;Q. Liu;F. Chafik;S. Pilorget;B. Lherron;H. Kothari;Y. Mignot;Y. Escarabajal;F. Allibert;K. Cheng;B. Doris
Author_Institution :
CEA LETI, IBM Research at Albany NanoTech, 257 Fuller Rd, NY, 12203 USA
Abstract :
This paper analyses the impact of 10nm Si cap layer for UTBB pFET eSiGe, with 35% Ge in channel and source/drain. For the first time, it is found that this Si cap can improve both access resistance and hole mobility in narrow structures.
Keywords :
"Silicon","Silicon germanium","Performance evaluation","Stress","Logic gates","Uniaxial strain"
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE
DOI :
10.1109/S3S.2015.7333544
