Title :
10nm Gate-length junctionless gate-all-around (JL-GAA) FETs based 8T SRAM design under process variation using a cross-layer simulation
Author :
Luhao Wang;Alireza Shafaei;Shuang Chen;Yanzhi Wang;Shahin Nazarian;Massoud Pedram
Author_Institution :
Department of Electrical Engineering, University of Southern California, Los Angeles CA 90089, USA
Abstract :
Gate-all-around (GAA) FETs is proposed as a choice for deeply scaled MOSFETs beyond the 10 nm technology node. In this paper, we present a device and circuit (8T SRAM) co-simulation work based on Junctionless-GAA (JL-GAA) FETs. The same doping concentration level in channel and source/drain can mitigate fabrication complexity and process variability. The 8T SRAM monte carlo simulation results considering process variations shows JL-GAA FETs can reliably operate at low supply voltage.
Keywords :
"Logic gates","Random access memory","Cross layer design","Monte Carlo methods"
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE
DOI :
10.1109/S3S.2015.7333552
