DocumentCode
3695563
Title
Scheduling for semiconductor assembly and test manufacturing enterprise
Author
Yaoguang Hu;Jiawei Ke;Jiawei Yan;Jingqian Wen
Author_Institution
School of Mechanical Engineering, Beijing Institute of Technology, China
fYear
2015
fDate
6/1/2015 12:00:00 AM
Firstpage
891
Lastpage
896
Abstract
Semiconductor assembly and test manufacturing enterprise belong to the model of multi-specification and small-batch. It´s a great challenge to make a production planning under uncertainty product categories and batches. Furthermore, product delivery time is very strict in the enterprise. Consequently, it´s a key issue to develop a reasonable production planning to ensure the timely completion of the production tasks in the actual production environment. With the analysis of the production process, burn-in process is the common process from different production lines. Burn-in process has several different devices for the burn-in of different products. This paper focuses on the key process batch scheduling problem. The problem is formulated into Integer Linear Programming (ILP), considering the constraints of devices, production capacity and delivery time. The optimization goal of the model is to minimize the production time. Firstly, heuristics is used to solve the order batching and the batch sorting. And then the adaptable genetic algorithm is put forward to solve the ILP. The proposed method is demonstrated by an experimental case within acceptable computational time. Result analysis verifies the validity of the algorithm and implements production planning optimization.
Keywords
"Job shop scheduling","Assembly","Production planning","Optimization","Genetic algorithms"
Publisher
ieee
Conference_Titel
Industrial Electronics and Applications (ICIEA), 2015 IEEE 10th Conference on
Type
conf
DOI
10.1109/ICIEA.2015.7334236
Filename
7334236
Link To Document