Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner

In this paper, an alternative fabrication approach to realize a via-last through-Si-via (TSV) for 3D chip stacking is proposed. Two deep silicon etching process (BOSCH) are implemented respectively for TSV´s liner and metal layers in order to avoid the critical process to open the contact at the bottom of Si via. Moreover, Parylene-HT is utilized for achieving highly uniformity, high-step-coverage liner. Vias was filled with a solder by a vacuum-assisted filling system. TSVs with dimensions of 6 µm × 22 µm (diameter×height) with 1.5-µm-thick Parylene-HT insulation layer were demonstrated using the proposed approach. Inspection of the fabricated TSV structure is conducted and results are reported.