Stress management strategy to limit die curvature during silicon interposer integration

Die-level warpage is a challenging issue affecting silicon interposer assembly yield. Stress management strategies are required to compensate residual and thermo-mechanical stress occurring during silicon interposer integration and die stacking processes. In this work, die-level curvature is measured using shadow moiré interferometry during a thermal cycle at several process steps. Finite element modeling aims at understanding the curvature behavior observed experimentally and then at proposing warpage compensation strategy. It is found that back-side dielectrics deposited at low-temperature have a critical impact on die curvature magnitude, compared to other layers typically found in Si interposer. On the contrary, organic passivation plays a minor role despite a high coefficient of thermal expansion. Experiments are carried out on Si-bulk and SOI substrates: in the case of SOI substrates, optimized compressive stress regime in the BS layers counteracts the residual stress in front-side layers, especially the compressive stress of the BOX alone. This configuration puts under appropriate conditions a large silicon interposer for subsequent packaging steps.