DocumentCode :
3695987
Title :
A Parallel and Reconfigurable United Architecture for Fibonacci and Galois LFSR
Author :
Wei Li;Xuan Yang
Author_Institution :
State-Key Lab. of ASIC &
Volume :
1
fYear :
2015
Firstpage :
203
Lastpage :
206
Abstract :
The parallel reconfigurable and united architecture of LFSR is represented to improve the speed, flexibility and security of communication system and cipher algorithms. It can be reconfigured to Fibonacci LFSRs and Galois LFSRs according to different applications. The random lengths and feedback taps can be achieved to meet the demands of different applications. The parallel updating method has an obvious advantage on speed and efficiency. Furthermore, the flexibility and complexity increases the security of the communication system and cipher algorithms.
Keywords :
"Ciphers","Algorithm design and analysis","Hardware","Delays","Computer architecture","Mathematical model"
Publisher :
ieee
Conference_Titel :
Intelligent Human-Machine Systems and Cybernetics (IHMSC), 2015 7th International Conference on
Print_ISBN :
978-1-4799-8645-3
Type :
conf
DOI :
10.1109/IHMSC.2015.265
Filename :
7334686
Link To Document :
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