Body-biased operation for improved MEM relay energy efficiency

The energy efficiency of complementary metal-oxide semiconductor (CMOS) logic circuits is fundamentally limited by the off-state leakage (Ioff) of the transistors [1]. Mechanical switches can achieve zero Ioff and hence can overcome this limit, in principle; therefore, scaled relay technologies recently have been investigated for ultra-low-power digital integrated-circuit (IC) applications [2]. In general, IC design involves a trade-off between operating energy, signal propagation delay, and die area (cost); design optimization aims to minimize one of these metrics given constraints on the other two. The methodology for co-optimizing the operating voltage and threshold voltage to minimize energy for a given delay in a fixed CMOS process (e.g. minimally sized transistors) has been well established [3]. In this work, a similar methodology is described for scaled logic relay technology.