Sub-5 nm gap formation for low power NEM switches

To utilize nanoelectromechanical (NEM) switches for ultra-low power applications, sub-1 V actuation is one of the most important challenges to overcome [1-4]. We develop a CMOS-compatible technique that introduces ultra-small air gaps (<5 nm) for lateral NEM switches to achieve zero-leakage and zero-crowbar-current circuits operating at sub-1 V. Ultra-small gap formation is achieved using growth/transfer of thin film/2D materials as sacrificial material before beam release. The gap size can be well controlled by the thickness of the thin film/2D materials. The lateral NEM switch has a single-pole double-throw configuration consisting of a freely suspended cantilever and two pairs of gate/drain electrodes placed symmetrically on both sides (Fig. 1a). The NEM operation was simulated using the Coventor MEMS+ software with Brick element model [6]. The length, width, and thickness of the poly-Si beam are 50, 1 and 1 μm, respectively. The initial gap between the beam and the gate (gbg) is 0.25 μm, and the gap between the beam and the drain (gbd) ranges from 1 to 40 nm. Fig. 1b shows that for gbd< (1/3)gbg, the pull-in voltage of the NEM switch decreases efficiently by shrinking gbd. In order to obtain sub-1 V switching, the contact gap gbd has to be minimized to sub-5 nm, which is difficult to achieve in the lateral NEM structure using a “top-down” pattern-and-etch approach.